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-rw-r--r--patches/source/glibc/glibc.6a824767.dont.assert.on.older.intel.cpus.diff32
1 files changed, 32 insertions, 0 deletions
diff --git a/patches/source/glibc/glibc.6a824767.dont.assert.on.older.intel.cpus.diff b/patches/source/glibc/glibc.6a824767.dont.assert.on.older.intel.cpus.diff
new file mode 100644
index 00000000..a3d1b147
--- /dev/null
+++ b/patches/source/glibc/glibc.6a824767.dont.assert.on.older.intel.cpus.diff
@@ -0,0 +1,32 @@
+From 6a824767d8948faf10d8d3a602eb4f2a59431601 Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Wed, 12 Oct 2016 08:22:52 -0700
+Subject: [PATCH] X86: Don't assert on older Intel CPUs [BZ #20647]
+
+Since the maximum CPUID level of older Intel CPUs is 1, change
+handle_intel to return -1, instead of assert, when the maximum
+CPUID level is less than 2.
+
+ [BZ #20647]
+ * sysdeps/x86_64/cacheinfo.c (handle_intel): Return -1 if the
+ maximum CPUID level is less than 2.
+
+diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
+index cf4f64b..35268e8 100644
+--- a/sysdeps/x86_64/cacheinfo.c
++++ b/sysdeps/x86_64/cacheinfo.c
+@@ -259,7 +259,9 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
+ static long int __attribute__ ((noinline))
+ handle_intel (int name, unsigned int maxidx)
+ {
+- assert (maxidx >= 2);
++ /* Return -1 for older CPUs. */
++ if (maxidx < 2)
++ return -1;
+
+ /* OK, we can use the CPUID instruction to get all info about the
+ caches. */
+--
+2.9.3
+
+