| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | academic/verilator: Added (Verilog HDL Simulator)....Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org> |   Charles Daniels | 2020-03-20 | 4 | -0/+140 |
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