Commit message (Expand) | Author | Age | Files | Lines | |
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* | academic/verilator: Fixed dep info...Signed-off-by: Matteo Bernardini <ponce@slackbuilds.org> | Matteo Bernardini | 2021-04-18 | 1 | -1/+1 |
* | academic/verilator: Added (Verilog HDL Simulator)....Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org> | Charles Daniels | 2020-03-20 | 4 | -0/+140 |