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| author |   Charles Daniels <charles [at] cdaniels [dot] net> | 2020-03-20 19:30:05 +0700 |
|---|---|---|
| committer |   Willy Sudiarto Raharjo <willysr@slackbuilds.org> | 2020-03-20 19:30:05 +0700 |
| commit | ab05ac3f2e155e5b8bcff71ba1499b28fa70f825 (patch) | |
| tree | 4320c3f751a71ae6c05d377c000b3d73f3e18113 /academic/verilator/verilator.info | |
| parent | f6bf1970803b476ceb857e28e8b7b1bcce7c01b0 (diff) | |
| download | slackbuilds-ab05ac3f2e155e5b8bcff71ba1499b28fa70f825.tar.gz slackbuilds-ab05ac3f2e155e5b8bcff71ba1499b28fa70f825.tar.xz | |
academic/verilator: Added (Verilog HDL Simulator).
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'academic/verilator/verilator.info')
| -rw-r--r-- | academic/verilator/verilator.info | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/academic/verilator/verilator.info b/academic/verilator/verilator.info new file mode 100644 index 0000000000..b67785a98d --- /dev/null +++ b/academic/verilator/verilator.info @@ -0,0 +1,10 @@ +PRGNAM="verilator" +VERSION="4.030" +HOMEPAGE="https://www.veripool.org/wiki/verilator" +DOWNLOAD="https://www.veripool.org/ftp/verilator-4.030.tgz" +MD5SUM="f412f817a8eeb142f6d27684e5fd4809" +DOWNLOAD_x86_64="" +MD5SUM_x86_64="" +REQUIRES="python3" +MAINTAINER="Charles Daniels" +EMAIL="charles [at] cdaniels [dot] net" |