| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | development/yosys: Added (A framework for Verilog RTL synthesis)...Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org> |   William PC | 2022-11-05 | 1 | -0/+22 |
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