| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | academic/verilator: Added (Verilog HDL Simulator). |   Charles Daniels | 2020-03-20 | 1 | -0/+9 |
| Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org> | |||||
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