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| author |   Fellype do Nascimento <fellype (at) gmail (dot) com> | 2020-01-12 10:51:49 +0700 |
|---|---|---|
| committer |   Willy Sudiarto Raharjo <willysr@slackbuilds.org> | 2020-01-12 10:51:49 +0700 |
| commit | a80c00941b261df58a7f8da1015e2207113ed8d0 (patch) | |
| tree | 6710925104901a058150f7a986547786dbf74fe7 /development/adms/README | |
| parent | 15570288a5c3a72bdd6b0dc4d291f8b408f88192 (diff) | |
| download | slackbuilds-a80c00941b261df58a7f8da1015e2207113ed8d0.tar.gz slackbuilds-a80c00941b261df58a7f8da1015e2207113ed8d0.tar.xz | |
development/adms: Added (An automatic device model synthesizer).
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'development/adms/README')
| -rw-r--r-- | development/adms/README | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/development/adms/README b/development/adms/README new file mode 100644 index 0000000000..06f8f88d79 --- /dev/null +++ b/development/adms/README @@ -0,0 +1,6 @@ +ADMS is a code generator for the Verilog-AMS language + +ADMS is a code generator that converts electrical compact device models specified +in high-level description language into ready-to-compile C code for the API of spice +simulators. Based on transformations specified in XML language, ADMS transforms +Verilog-AMS code into other target languages. |